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256k x 36/512k x 18 synchronous burst flowthrough sram cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 may 17, 2000 features ? fast access times: 6.0, 6.5, 7.0, and 8.0 ns fast clock speed: 150, 133, 117, and 100 mhz 1 ns set up time and hold time fast oe access times: 3.5 ns and 4.0 ns 3.3v ?5% and +10% power supply 3.3v or 2.5v i/o supply 5v tolerant inputs except i/os clamp diodes to v ss at all inputs and outputs common data inputs and data outputs byte write enable and global write control multiple chip enables for depth expansion: three chip enables for ta(gvti)/a(cy) package version and two chip enables for b(gvti)/bg(cy) and t(gvti)/aj(cy) package versions address pipeline capability address, data and control registers internally self-timed write cycle burst control pins (interleaved or linear burst se- quence) automatic power-down for portable applications jtag boundary scan for b and t package version low profile 119-bump, 14-mm x 22-mm pbga (ball grid array) and 100-pin tqfp packages functional description the cypress synchronous burst sram family employs high- speed, low-power cmos designs using advanced triple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high-valued resistors. the gvt71256b36/cy7c1361a and gvt71512b18/ cy7c1363a srams integrate 262,144x36 and 524,288x18 sram cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. all synchro- nous inputs are gated by registers controlled by a positive- edge-triggered clock input (clk). the synchronous inputs in- clude all addresses, all data inputs, address-pipelining chip enable (ce ), depth-expansion chip enables (ce 2 and ce 2 ), burst control inputs (adsc , adsp , and adv ), write enables (bwa , bwb , bwc , bwd , and bwe ), and global write (gw ). however, the ce 2 chip enable input is only available for ta(gvti)/a(cy) package version. asynchronous inputs include the output enable (oe ) and burst mode control (mode). the data outputs (q), enabled by oe , are also asynchronous. addresses and chip enables are registered with either ad- dress status processor (adsp ) or address status controller (adsc ) input pins. subsequent burst addresses can be inter- nally generated as controlled by the burst advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate self-timed write cycle. write cycles can be one to four bytes wide as controlled by the write control inputs. individual byte write allows individual byte to be written. bwa controls dqa. bwb controls dqb. bwc controls dqc. bwd controls dqd. bwa , bwb , bwc , and bwd can be active only with bwe being low. gw being low causes all bytes to be written. the x18 version only has 18 data inputs/outputs (dqa and dqb) along with bwa and bwb (no bwc , bwd , dqc, and dqd). for the b(gvti)/bg(cy) and t(gvti)/aj(cy) package ver- sions, four pins are used to implement jtag test capabilities: test mode select (tms), test data-in (tdi), test clock (tck), and test data-out (tdo). the jtag circuitry is used to serially shift data to and from the device. jtag inputs use lvttl/lvcmos levels to shift data during this testing mode of operation. the ta package version does not offer the jtag capability. the gvt71256b36 and gvt71512b18 operate from a +3.3v power supply. all inputs and outputs are lvttl compatible. selection guide 7c1361a-150 7c1363a-150 71256b36-6 71512b18-6 7c1361a-133 7c1363a-133 71256b36-6.5 71512b18-6.5 7c1361a-117 7c1363a-117 71256b36-7 71512b18-7 7c1361a-100 7c1363a-100 71256b36-8 71512b18-8 maximum access time (ns) 6.0 6.5 7.0 8.0 maximum operating current (ma) 400 360 320 270 maximum cmos standby current (ma) 10 10 10 10
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 2 notes: 1. the functional block diagram illustrates simplified device operation. see truth table, pin descriptions, and timing diagrams for detailed information. 2. ce 2 is for aj/ta version only. dq dq bwc# bwe# bwd# byte c write byte d write oe# byte c write adsp# adsc# address register binary counter & logic clr a a1-a0 adv# mode 256k x 9 x 4 sram array output buffers input register byte d write dqa,dqb dqc,dqd dq dq dq bwa# bwb# gw# byte a write byte b write clk byte b write byte a write enable power down logic zz 16 ce# ce2 [2] ce2# 256k x 36 (cy7c1361a/gvt71256b36) functional block diagram [1] 512k x 18 (cy7c1363a/gvt71512b18)functional block diagram dq dq bwb# bwe# bwa# gw# byte b write byte a write oe# byte b write adsp# adsc# address register binary counter & logic clr a a1-a0 adv# mode 512k x 9 x 2 sram array output buffers input register byte a write dqa,d qb dq enable power down logic zz 17 ce# ce2 [2] ce2#
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 3 pin configurations cy7c1361a/gvt71256b36 100-pin tqfp ta version 100 99 98 97 96 95 94 93 92 91 90 89 88 1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40 41 42 43 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 a a ce# adsc# adsp# adv# clk oe# a a vcc vss gw# bwe# ce2# dqb dqb dqb vss vccq dqb dqb dqa dqa vccq vss dqa dqa vss nc vcc zz a a a a a1 a0 vss vcc a a a a a mode nc nc nc a a a ce2 bwd# bwc# bwb# bwa# vccq vss dqb dqb dqb dqb dqa dqa dqa dqa dqa vss vccq dqc dqc dqc vss vccq dqc dqc dqd dqd vccq vss dqd dqd vss nc vcc nc vccq vss dqc dqc dqc dqc dqd dqd dqd dqd dqd vss vccq 100-pin tqfp 100 99 98 97 96 95 94 93 92 91 90 89 88 1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40 41 42 43 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 a a ce# adsc# adsp# adv# clk oe# a a vcc vss gw# bwe# a dqb dqb dqb vss vccq dqb dqb dqa dqa vccq vss dqa dqa vss nc vcc zz a a a a a1 a0 vss vcc a a a a a mode tms tdi tdo tck a a ce2 bwd# bwc# bwb# bwa# vccq vss dqb dqb dqb dqb dqa dqa dqa dqa dqa vss vccq dqc dqc dqc vss vccq dqc dqc dqd dqd vccq vss dqd dqd vss nc vcc nc vccq vss dqc dqc dqc dqc dqd dqd dqd dqd dqd vss vccq t(aj) package version ta(a) package version 256kx36 100-pin tqfp 100-pin tqfp 10 0 99 98 97 96 95 94 93 92 91 90 89 88 1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40 41 42 43 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 a a ce# bwb# bwa# adsc# adsp# adv# clk oe# a a vcc vss gw# bwe# a dqa dqa dqa vss vccq dqa dqa dqa dqa vccq vss dqa dqa a nc nc vccq vss nc nc nc vss vccq nc nc nc vss nc vcc zz dqb dqb vss vccq dqb dqb dqb dqb vccq vss dqb dqb dqb nc nc nc vccq vss nc nc nc vcc nc vss nc vss vccq nc nc nc a a a a a1 a0 vss vcc a a a a a mode a a ce2 nc nc tms tdi tdo tck cy7c1363a/gvt71512b18 t(aj) package version ta(a) package version 100-pin tqfp ta version 100 99 98 97 96 95 94 93 92 91 90 89 88 1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40 41 42 43 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 a a ce# bwb# bwa# adsc# adsp# adv# clk oe# a a vcc vss gw# bwe# ce2# dqa dqa dqa vss vccq dqa dqa dqa dqa vccq vss dqa dqa a nc nc vccq vss nc nc nc vss vccq nc nc nc vss nc vcc zz dqb dqb vss vccq dqb dqb dqb dqb vccq vss dqb dqb dqb nc nc nc vccq vss nc nc nc vcc nc vss nc vss vccq nc nc nc a a a a a1 a0 vss vcc a a a a a mode a a ce2 nc nc nc nc nc a 512kx18 100-pin tqfp
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 4 pin configurations (continued) cy7c1361a/gvt71256b36 1234567 a v ccq aaadsp aav ccq b nc ce 2 aadsc aanc c nc a a v cc aanc d dqc dqc v ss nc v ss dqb dqb e dqc dqc v ss ce v ss dqb dqb f v ccq dqc v ss oe v ss dqb v ccq g dqc dqc bwc adv bwb dqb dqb h dqc dqc v ss gw v ss dqb dqb j v ccq v cc nc v cc nc v cc v ccq k dqd dqd v ss clk v ss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ccq dqd v ss bwe v ss dqa v ccq n dqd dqd v ss a1 v ss dqa dqa p dqd dqd v ss a0 v ss dqa dqa r nc a mode v cc nc a nc t nc nc a a a nc zz u v ccq tms tdi tck tdo nc v ccq cy7c1361a/gvt71256b36 1234567 a v ccq aaadsp aav ccq b nc ce 2 aadsc aanc c nc a a v cc aanc d dqb nc v ss nc v ss dqa nc e nc dqb v ss ce v ss nc dqa f v ccq nc v ss oe v ss dqa v ccq g nc dqb bwb adv v ss nc dqa h dqb nc v ss gw v ss dqa nc j v ccq v cc nc v cc nc v cc v ccq k nc dqb v ss clk v ss nc dqa l dqb nc v ss nc bwa dqa nc m v ccq dqb v ss bwe v ss nc v ccq n dqb nc v ss a1 v ss dqa nc p nc dqb v ss a0 v ss nc dqa r nc a mode v cc nc a nc t ncaaaaazz u v ccq tms tdi tck tdo nc v ccq 512kx18 119-ball bga top view 256kx36 119-ball bga top view
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 5 256k x 36 pin descriptions x36 pbga pins x36 qfp pins pin name type description 4p 4n 2a, 3a, 5a, 6a, 3b, 5b, 6b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 92 (a/t version) 43 (aj/ta ver- sion) a0 a1 a input- synchronous addresses: these inputs are registered and must meet the set- up and hold times around the rising edge of clk. the burst counter generates internal addresses associated with a0 and a1, during burst cycle and wait cycle. 5l 5g 3g 3l 93 94 95 96 bwa bwb bwc bwd input- synchronous byte write: a byte write is low for a write cycle and high for a read cycle. bwa controls dqa. bwb controls dqb. bwc con- trols dqc. bwd controls dqd. data i/o are high impedance if either of these inputs are low, conditioned by bwe being low. 4m 87 bwe input- synchronous write enable: this active low input gates byte write operations and must meet the set-up and hold times around the rising edge of clk. 4h 88 gw input- synchronous global write: this active low input allows a full 36-bit write to occur independent of the bwe and bwn lines and must meet the set up and hold times around the rising edge of clk. 4k 89 clk input- synchronous clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. all syn- chronous inputs must meet set up and hold times around the clock ? s rising edge. 4e 98 ce input- synchronous chip enable: this active low input is used to enable the device and to gate adsp . 2b 97 ce 2 input- synchronous chip enable: this active high input is used to enable the device. (not available for pbga) 92 (for aj/ta version only) ce 2 input- synchronous chip enable: this active low input is used to enable the device. not available for b and t package versions. 4f 86 oe input output enable: this active low asynchronous input enables the data output drivers. 4g 83 adv input- synchronous address advance: this active low input is used to control the internal burst counter. a high on this pin generates wait cycle (no address advance). 4a 84 adsp input- synchronous address status processor: this active low input, along with ce being low, causes a new external address to be registered and a read cycle is initiated using the new address. 4b 85 adsc input- synchronous address status controller: this active low input causes device to be deselected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs. 3r 31 mode input- static mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. 7t 64 zz input- asynchro- nous snooze: this active high input puts the device in low power consumption standby mode. for normal operation, this input has to be either low or nc (no connect).
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 6 (a) 6p, 7p, 7n, 6n, 6m, 6l, 7l, 6k, 7k, (b) 7h, 6h, 7g, 6g, 6f, 6e, 7e, 7d, 6d, (c) 2d, 1d, 1e, 2e, 2f, 1g, 2g, 1h, 2h, (d) 1k, 2k, 1l, 2l, 2m, 1n, 2n, 1p, 2p (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 dqa dqb dqc dqd input/ output data inputs/outputs: first byte is dqa. second byte is dqb. third byte is dqc. fourth byte is dqd. input data must meet set up and hold times around the rising edge of clk. 2u 3u 4u 38 39 43 for bg/b and a/t version tms tdi tck input ieee 1149.1 test inputs. lvttl-level inputs. not available for aj/ta package version. 5u 42 for bg/b and a/t version tdo output ieee 1149.1 test output. lvttl-level output. not available for aj/ta package version. 4c, 2j, 4j, 6j, 4r 15, 41,65, 91 v cc supply core power supply: +3.3v ? 5% and +10% 3d, 5d, 3e, 5e, 3f, 5f, 3h, 5h, 3k, 5k, 3m, 5m, 3n, 5n, 3p, 5p 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss ground ground: gnd. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u 4, 11, 20, 27, 54, 61, 70, 77 v ccq i/o supply output buffer supply: +2.5v or +3.3v. 1b, 7b, 1c, 7c, 4d, 3j, 5j, 4l, 1r, 5r, 7r, 1t, 2t, 6t, 6u 14, 16, 66 38, 39, 42 for aj/ta version nc - no connect: these signals are not internally connected. user can leave it floating or connect it to v cc or v ss . 256k x 36 pin descriptions (continued) x36 pbga pins x36 qfp pins pin name type description 512k x 18 pin descriptions x18 pbga pins x18 qfp pins pin name type description 4p 4n 2a, 3a, 5a, 6a, 3b, 5b, 6b, 2c, 3c, 5c, 6c, 2r, 6r, 2t, 3t, 5t, 6t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 92 (a/t version) 43 (aj/ta ver- sion) a0 a1 a input- synchronous addresses: these inputs are registered and must meet the set up and hold times around the rising edge of clk. the burst counter generates internal addresses associated with a0 and a1, during burst cycle and wait cycle. 5l 3g 93 94 bwa bwb input- synchronous byte write enables: a byte write enable is low for a write cycle and high for a read cycle. bwa controls dqa. bwb controls dqb. data i/o are high impedance if either of these inputs are low, conditioned by bwe being low. 4m 87 bwe input- synchronous write enable: this active low input gates byte write operations and must meet the set up and hold times around the rising edge of clk.
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 7 4h 88 gw input- synchronous global write: this active low input allows a full 18-bit write to occur independent of the bwe# and wen# lines and must meet the set up and hold times around the rising edge of clk. 4k 89 clk input- synchronous clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. all syn- chronous inputs must meet set up and hold times around the clock ? s rising edge. 4e 98 ce input- synchronous chip enable: this active low input is used to enable the device and to gate adsp . 2b 97 ce 2 input- synchronous chip enable: this active high input is used to enable the device. (not available for pbga) 92 (for aj/ta version only) ce 2 input- synchronous chip elnable: this active low input is used to enable the device. not available for b and t package versions. 4f 86 oe input output enable: this active low asynchronous input enables the data output drivers. 4g 83 adv input- synchronous address advance: this active low input is used to control the internal burst counter. a high on this pin generates wait cycle (no address advance). 4a 84 adsp input- synchronous address status processor: this active low input, along with ce being low, causes a new external address to be registered and a read cycle is initiated using the new address. 4b 85 adsc input- synchronous address status controller: this active low input causes device to be deselected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs. 3r 31 mode input- static mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. 7t 64 zz input-asyn- chronous snooze: this active high input puts the device in low power consumption standby mode. for normal operation, this input has to be either low or nc (no connect). (a) 6d, 7e, 6f, 7g, 6h, 7k, 6l, 6n, 7p (b) 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 dqa dqb input/ output data inputs/outputs: low byte is dqa. high byte is dqb. input data must meet setup and hold times around the rising edge of clk. 2u 3u 4u 38 39 43 for b and t ver- sion tms tdi tck input ieee 1149.1 test inputs. lvttl-level inputs. not available for aj/ta package version. 5u 42 for b and t ver- sion tdo output ieee 1149.1 test output. lvttl-level output. not available for aj/ta package version. 4c, 2j, 4j, 6j, 4r 15, 41,65, 91 v cc supply core power supply: +3.3v ? 5% and +10% 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss ground ground: gnd. 512k x 18 pin descriptions (continued) x18 pbga pins x18 qfp pins pin name type description
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 8 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u 4, 11, 20, 27, 54, 61, 70, 77 v ccq i/o supply output buffer supply: +2.5v or +3.3v. 1b, 7b, 1c, 7c, 2d, 4d, 7d, 1e, 6e, 2f, 1g, 6g, 2h, 7h, 3j, 5j, 1k, 6k, 2l, 4l, 7l, 6m, 2n, 7n, 1p, 6p, 1r, 5r, 7r, 1t, 4t, 6u 1-3, 6, 7, 14, 16, 25, 28-30, 51- 53, 56, 57, 66, 75, 78, 79, 80, 95, 96 38, 39, 42 for aj/ta version nc - no connect: these signals are not internally connected. user can leave it floating or connect it to v cc or v ss . 512k x 18 pin descriptions (continued) x18 pbga pins x18 qfp pins pin name type description burst address table (mode = nc/v cc ) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a00 a...a11 a...a10 a...a10 a...a11 a...a00 a...a01 a...a11 a...a10 a...a01 a...a00 burst address table (mode = gnd) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a10 a...a11 a...a00 a...a10 a...a11 a...a00 a...a01 a...a11 a...a00 a...a01 a...a10
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 9 truth table [3, 4, 5, 6, 7, 8, 9] operation address used ce ce 2 ce 2 adsp adsc adv write oe clk dq deselected cycle, power down none h x x x l x x x l-h high-z deselected cycle, power down none l x l l x x x x l-h high-z deselected cycle, power down none l h x l x x x x l-h high-z deselected cycle, power down none l x l h l x x x l-h high-z deselected cycle, power down none l h x h l x x x l-h high-z read cycle, begin burst external l l h l x x x l l-h q read cycle, begin burst external l l h l x x x h l-h high-z write cycle, begin burst external l l h h l x l x l-h d read cycle, begin burst external l l h h l x h l l-h q read cycle, begin burst external l l h h l x h h l-h high-z read cycle, continue burst next x x x h h l h l l-h q read cycle, continue burst next x x x h h l h h l-h high-z read cycle, continue burst next h x x x h l h l l-h q read cycle, continue burst next h x x x h l h h l-h high-z write cycle, continue burst next x x x h h l l x l-h d write cycle, continue burst next h x x x h l l x l-h d read cycle, suspend burst current x x x h h h h l l-h q read cycle, suspend burst current x x x h h h h h l-h high-z read cycle, suspend burst current h x x x h h h l l-h q read cycle, suspend burst current h x x x h h h h l-h high-z write cycle, suspend burst current x x x h h h l x l-h d write cycle, suspend burst current h x x x h h l x l-h d partial truth table for read/write [10] function gw bwe bwa bwb bwc bwd read hhxxxx read hlhhhh write one byte h l l h h h write all bytes hlllll write all bytes lxxxxx notes: 3. x = ? don ? t care. ? h = logic high. l = logic low. for x36 product, write = l means [bwe + bwa *bwb *bwc *bwd ]*gw equals low. write = h means [bwe + bwa *bwb *bwc *bwd ]*gw equals high. for x18 product, write = l means [bwe + bwa *bwb ]*gw equals low. write = h means [bwe + bwa *bwb ]*gw equals high. 4. bwa enables write to dqa. bwb enables write to dqb. bwc enables write to dqc. bwd enables write to dqd. 5. all inputs except oe must meet set-up and hold times around the rising edge (low to high) of clk. 6. suspending burst generates wait cycle. 7. for a write operation following a read operation, oe must be high before the input data required set-up time plus high-z time for oe and staying high throughout the input data hold time. 8. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 9. adsp low along with chip being selected always initiates a read cycle at the l-h edge of clk. a write cycle can be performed by set ting write low for the clk l-h edge of the subsequent wait cycle. refer to write timing diagram for clarification. 10. for x18 product, there are only bwa and bwb .
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 10 ieee 1149.1 serial boundary scan (jtag) overview this device incorporates a serial boundary scan access port (tap). this port is designed to operate in a manner consistent with ieee standard 1149.1-1990 (commonly referred to as jtag), but does not implement all of the functions required for ieee 1149.1 compliance. certain functions have been modi- fied or eliminated because their implementation places extra delays in the critical speed path of the device. nevertheless, the device supports the standard tap controller architecture (the tap controller is the state machine that controls the taps operation) and can be expected to function in a manner that does not conflict with the operation of devices with ieee stan- dard 1149.1 compliant taps. the tap operates using lvttl/lvcmos logic level signaling. disabling the jtag feature it is possible to use this device without using the jtag feature. to disable the tap controller without interfering with normal operation of the device, tck should be tied low (v ss ) to pre- vent clocking the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be pulled up to v cc through a resistor. tdo should be left unconnected. upon power-up the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) tck - test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms - test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. tdi - test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruc- tion that is currently loaded in the tap instruction register (refer to figure 1 , tap controller state diagram). it is allowable to leave this pin unconnected if it is not used in an application. the pin is pulled up internally, resulting in a logic high level. tdi is connected to the most significant bit (msb) of any reg- ister. (see figure 2 .) tdo - test data out (output) the tdo output pin is used to serially clock data-out from the registers. the output that is active depending on the state of the tap state machine (refer to figure 1 , tap controller state diagram). output changes in response to the falling edge of tck. this is the output side of the serial registers placed be- tween tdi and tdo. tdo is connected to the least significant bit (lsb) of any register. (see figure 2 .) performing a tap reset the tap circuitry does not have a reset pin (trst , which is optional in the ieee 1149.1 specification). a reset can be performed for the tap controller by forcing tms high (v cc ) for five rising edges of tck and pre-loads the instruction reg- ister with the idcode command. this type of reset does not affect the operation of the system logic. the reset affects test logic only. at power-up, the tap is reset internally to ensure that tdo is in a high-z state. test access port (tap) registers overview the various tap registers are selected (one at a time) via the sequences of ones and zeros input to the tms pin as the tck is strobed. each of the taps registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on subsequent falling edge of tck. when a register is selected, it is connected between the tdi and tdo pins. instruction register the instruction register holds the instructions that are execut- ed by the tap controller when it is moved into the run test/idle or the various data register states. the instructions are three bits long. the register can be loaded when it is placed between the tdi and tdo pins. the parallel outputs of the instruction register are automatically preloaded with the idcode instruc- tion upon power-up or whenever the controller is placed in the test-logic reset state. when the tap controller is in the cap- ture-ir state, the two least significant bits of the serial instruc- tion register are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board-level serial test data path. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the device tap to another device in the scan chain with minimum delay. the bypass register is set low (vss) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional i/o pins (not counting the tap pins) on the device. this also includes a number of nc pins that are reserved for future needs. there are a total of 70 bits for x36 device and 51 bits for x18 device. the boundary scan register, under the con- trol of the tap controller, is loaded with the contents of the device i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the con- troller is moved to shift-dr state. the extest, sam- ple/preload and sample-z instructions can be used to capture the contents of the i/o ring. the boundary scan order table describes the order in which the bits are connected. the first column defines the bit ? s posi- tion in the boundary scan register. the msb of the register is connected to tdi, and lsb is connected to tdo. the second column is the signal name, the third column is the tqfp pin number, and the fourth column is the pbga bump number.
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 11 identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the device as described in the identification register definitions table. tap controller instruction set overview there are two classes of instructions defined in the ieee stan- dard 1149.1-1990; the standard (public) instructions and de- vice specific (private) instructions. some public instructions are mandatory for ieee 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the ieee 1149.1 conventions, it is not ieee 1149.1 compliant because some of the mandatory instructions are not fully implemented. the tap on this device may be used to monitor all input and i/o pads, but can not be used to load address, data, or control signals into the device or to preload the i/o buffers. in other words, the device will not perform ieee 1149.1 extest, in- test, or the preload portion of the sample/preload com- mand. when the tap controller is placed in capture-ir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shift-ir state the in- struction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction sets for this device are listed in the following tables. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in this device. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the device responds as if a sample/preload instruction has been loaded. there is one difference between two instruc- tions. unlike sample/preload instruction, extest places the device outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the id register when the controller is in cap- ture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in the instruction upon power-up and at any time the tap controller is placed in the test-logic reset state. sample-z if the high-z instruction is loaded in the instruction register, all output pins are forced to a high-z state and the boundary scan register is connected between tdi and tdo pins when the tap controller is in a shift-dr state. sample/preload sample/preload is an ieee 1149.1 mandatory instruction. the preload portion of the command is not implemented in this device, so the device tap controller is not fully ieee 1149.1-compliant. when the sample/preload instruction is loaded in the in- struction register and the tap controller is in the capture-dr state, a snap shot of the data in the device ? s input and i/o buffers is loaded into the boundary scan register. because the device system clock(s) are independent from the tap clock (tck), it is possible for the tap to attempt to capture the input and i/o ring contents while the buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results can not be expected. to guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the tap controller ? s capture setup plus hold time (t cs plus t ch ). the device clock input(s) need not be paused for any other tap operation except capturing the input and i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the bound- ary scan register between the tdi and tdo pins. because the preload portion of the command is not implemented in this device, moving the controller to the update-dr state with the sample/preload instruction loaded in the instruction reg- ister has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction reg- ister and the tap controller is in the shift-dr state, the bypass register is placed between tdi and tdo. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. reserved do not use these instructions. they are reserved for future use.
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 12 note: 11. the 0/1 next to each state represents the value at tms at the rising edge of tck. figure 1. tap controller state diagram [11] test-logic reset reun-test/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pau se -i r exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 13 figure 2. tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . x 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tdi tdi [12] tap electrical characteristics (20 c < t j < 110 c; v cc = 3.3v ? 0.2v and +0.3v unless otherwise noted) parameter description test conditions min. max. unit v ih input high (logic 1) voltage [13, 14] 2.0 v cc + 0.3 v v il input low (logic 0) voltage [13, 14] ? 0.3 0.8 v il i input leakage current 0v < v in < v cc ? 5.0 5.0 a il i tms and tdi input leakage current 0v < v in < v cc ? 30 30 a il o output leakage current output disabled, 0v < v in < v ccq ? 5.0 5.0 a v olc lvcmos output low voltage [13, 15] i olc = 100 a 0.2 v v ohc lvcmos output high voltage [13, 15] i ohc = 100 a v cc ? 0.2 v v olt lvttl output low voltage [13] i olt = 8.0 ma 0.4 v v oht lvttl output high voltage [13] i oht = 8.0 ma 2.4 v notes: 12. x = 69 for the x36 configuration; x = 50 for the x18 configuration. 13. all voltage referenced to v ss (gnd). 14. overshoot: v ih (ac)< v dd +1.5v for t< t khkh /2, undershoot:v il (ac)< ? 0.5v for t< t khkh /2, power-up: v ih < +3.6v and v cc < 3.135v and v ccq < 1.4v for t< 200 ms. 15. this parameter is sampled.
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 14 tap ac switching characteristics over the operating range [16, 17] parameter description min. max. unit clock t thth clock cycle time 20 ns f tf clock frequency 50 mhz t thtl clock high time 8 ns t tlth clock low time 8 ns output times t tlqx tck low to tdo unknown 0 ns t tlqv tck low to tdo valid 10 ns t dvt h tdi valid to tck high 5 ns t thdx tck high to tdi invalid 5 ns set-up times t mvth tms set-up 5 ns t cs capture set-up 5 ns hold times t thmx tms hold 5 ns t ch capture hold 5 ns notes: 16. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 17. test conditions are specified using the load in tap ac test conditions.
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 15 tap timing and test conditions (a) tdo c l =20 pf z 0 =50 ? gnd 1.5v 50 ? 3.0v v ss all input pulses 1.5v 1.5 ns 1.5 ns test clock (tck) t thth t thtl t tlth test mode select (tms) test data in (tdi) test data out (tdo) t mvth t thmx t dvth t thdx t tlqx t tlqv
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 16 identification register definitions instruction field 256k x 36 512k x 18 description revision number (31:28) xxxx xxxx reserved for revision number. device depth (27:23) 00110 00111 defines depth of 256k or 512k words. device width (22:18) 00100 00011 defines width of x36 or x18 bits. reserved (17:12) xxxxxx xxxxxx reserved for future use. cypress jedec id code (11:1) 00011100100 00011100100 allows unique identification of device vendor. id register presence indicator (0) 1 1 indicates the presence of an id register. scan register sizes register name bit size (x36) bit size (x18) instruction 3 3 bypass 1 1 id 32 32 boundary scan 70 51 instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all device outputs to high-z state. this instruction is not ieee 1149.1-compliant. idcode 001 preloads id register with vendor id code and places it between tdi and tdo. this instruction does not affect device operations. sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all device outputs to high-z state. reserved 011 do not use these instructions; they are reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. this instruction does not affect device operations. this instruction does not implement ieee 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use these instructions; they are reserved for future use. reserved 110 do not use these instructions; they are reserved for future use. bypass 111 places the bypass register between tdi and tdo. this instruction does not affect device operations.
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 17 boundary scan order (256k x 36) bit# signal name tqfp bump id 1a442r 2 a 45 3t 3 a 46 4t 4 a 47 5t 5a486r 6a493b 7a505b 8dqa516p 9dqa527n 10dqa536m 11 dqa 56 7l 12 dqa 57 6k 13 dqa 58 7p 14 dqa 59 6n 15 dqa 62 6l 16 dqa 63 7k 17 zz 64 7t 18 dqb 68 6h 19 dqb 69 7g 20 dqb 72 6f 21 dqb 73 7e 22 dqb 74 6d 23 dqb 75 7h 24 dqb 78 6g 25 dqb 79 6e 26 dqb 80 7d 27 a 81 6a 28 a 82 5a 29 adv 83 4g 30 adsp 84 4a 31 adsc 85 4b 32 oe 86 4f 33 bwe 87 4m 34 gw 88 4h 35 clk 89 4k 36 a 92 6b 37 bwa 93 5l 38 bwb 94 5g 39 bwc 95 3g 40 bwd 96 3l 41 ce 2 97 2b 42 ce 98 4e 43 a 99 3a 44 a 100 2a 45 dqc 1 2d 46 dqc 2 1e 47 dqc 3 2f 48 dqc 6 1g 49 dqc 7 2h 50 dqc 8 1d 51 dqc 9 2e 52 dqc 12 2g 53 dqc 13 1h 54 nc 14 5r 55 dqd 18 2k 56 dqd 19 1l 57 dqd 22 2m 58 dqd 23 1n 59 dqd 24 2p 60 dqd 25 1k 61 dqd 28 2l 62 dqd 29 2n 63 dqd 30 1p 64 mode 31 3r 65 a 32 2c 66 a 33 3c 67 a 34 5c 68 a 35 6c 69 a1 36 4n 70 a0 37 4p boundary scan order (256k x 36) bit# signal name tqfp bump id
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 18 boundary scan order (512k x 18) bit# signal name tqfp bump id 1 a 44 2r 2 a 45 2t 3 a 46 3t 4 a 47 5t 5 a 48 6r 6 a 49 3b 7 a 50 5b 8 dqa 58 7p 9 dqa 59 6n 10 dqa 62 6l 11 dqa 63 7k 12 zz 64 7t 13 dqa 68 6h 14 dqa 69 7g 15 dqa 72 6f 16 dqa 73 7e 17 dqa 74 6d 18 a 80 6t 19 a 81 6a 20 a 82 5a 21 adv 83 4g 22 adsp 84 4a 23 adsc 85 4b 24 oe 86 4f 25 bwe 87 4m 26 gw 88 4h 27 clk 89 4k 28 a 92 6b 29 bwa 93 5l 30 bwb 94 3g 31 ce 2 97 2b 32 ce 98 4e 33 a 99 3a 34 a 100 2a 35 dqb 8 1d 36 dqb 9 2e 37 dqb 12 2g 38 dqb 13 1h 39 nc 14 5r 40 dqb 18 2k 41 dqb 19 1l 42dqb222m 43 dqb 23 1n 44 dqb 24 2p 45 mode 31 3r 46 a 32 2c 47 a 33 3c 48 a 34 5c 49 a 35 6c 50 a1 36 4n 51 a0 37 4p boundary scan order (512k x 18) bit# signal name tqfp bump id
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 19 maximum ratings (above which the useful life may be impaired. for user guide- lines only, not tested.) voltage on v cc supply relative to v ss ......... ? 0.5v to +4.6v v in ............................................................ ? 0.5v to v cc +0.5v storage temperature (plastic)........................ ? 55 c to +150 junction temperature ..................................................+150 power dissipation .......................................................... 1.0w short circuit output current ....................................... 50 ma . operating range range ambient temperature [10] v cc com ? l 0 c to + 70 c 3.3v ? 5%/+10% electrical characteristics over the operating range parameter description test conditions min. max. unit v ihd input high (logic 1) voltage [13, 19] data inputs (dqx) 2.0 v cc +0.3 v v ih all other inputs 2.0 4.6 v v il input low (logic 0) voltage [13, 19] ? 0.5 0.8 v il i input leakage current [13, 19] 0v < v in < v cc ? 5 5 a il i mode and zz input leakage current [20] 0v < v in < v cc ? 30 30 a il o output leakage current output(s) disabled, 0v < v out < v cc ? 5 5 a v oh output high voltage [13] i oh = ? 5.0 ma 2.4 v v ol output low voltage [13] i ol = 8.0 ma 0.4 v v cc supply voltage [13] 3.135 3.6 v v ccq i/o supply voltage (3.3v) [13] 3.135 v cc v v ccq i/o supply voltage (2.5v) [13] 2.375 v cc v parameter description conditions typ. -6 -6.5 -7 -8 unit i cc power supply current: operating [21, 22, 23] device selected; all inputs < v il or > v ih ; cycle time > t kc min.; v cc = max.; outputs open 150 400 360 320 270 ma i sb2 cmos standby [22, 23] device deselected; v cc = max.; all inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; clk frequency = 0 510101010ma i sb3 ttl standby [22, 23] device deselected; all inputs < v il or > v ih ; all inputs static; v cc = max.; clk frequency = 0 15 30 30 30 30 ma i sb4 clock running [22, 23] device deselected; all inputs < v il or > v ih ; v cc = max.; clk cycle time > t kc min. 40 90 80 70 60 ma thermal consideration parameter description conditions tqfp typ. unit ja thermal resistance - junction to ambient still air, soldered on 4.25 x 1.125 inch 4-layer pcb 25 c/w jc thermal resistance - junction to case 9 c/w notes: 18. t a is the case temperature. 19. overshoot: v ih < +6.0v for t < t kc /2. undershoot: v il < ? 2.0v for t < t kc /2. 20. output loading is specified with c l = 5 pf as in ac test loads. 21. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 22. ? device deselected ? means the device is in power-down mode as defined in the truth table. ? device selected ? means the device is active. 23. typical values are measured at 3.3v, 25 c and 20-ns cycle time.
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 20 capacitance parameter description test conditions typ. max. unit c i input capacitance [15] t a = 25 c, f = 1 mhz, v cc = 3.3v 5 7 pf c o input/output capacitance (dq) [15] 7 8 pf typical output buffer characteristics output high voltage pull-up current output low voltage pull-down current v oh (v) i oh ( ma ) min. i oh (ma) max. v ol (v) i ol (ma) min. i l ( ma ) max. ? 0.5 ? 38 ? 105 ? 0.5 0 0 0 ? 38 ? 105 0 0 0 0.8 ? 38 ? 105 0.4 10 20 1.25 ? 26 ? 83 0.8 20 40 1.5 ? 20 ? 70 1.25 31 63 2.3 0 ? 30 1.6 40 80 2.7 0 ? 10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 ac test loads and waveforms (3.3v i/o) ac test loads and waveforms (2.5v i/o) dq r = 317 ? r = 351 ? 5pf (a) (b) dq r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses [13] 3.0v 0v 90% 10% 90% 10% 1.0 ns 1.0 ns (c) (a) dq r l = 50 ? z 0 = 50 ? v t = 1.25v all input pulses 2.5v 0v 90% 10% 90% 10% 1.0 ns 1.0 ns (c)
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 21 switching characteristics over the operating range [24] description -6 -6.5 -7 -8 parameter min. max. min. max. min. max. min. max. unit clock t kc clock cycle time 6.7 7.5 8.5 10 ns t kh clock high time 2.5 2.5 3.0 3.5 ns t kl clock low time 2.5 2.5 3.0 3.5 ns output times t kq clock to output valid v ccq =3.3v 6.0 6.5 7.0 8.0 ns v ccq =2.5v 6.5 7.0 7.5 9.0 ns t kqx clock to output invalid 2 2 2 2 ns t kqlz clock to output in low-z [15, 20, 25] 0 0 0 0 ns t kqhz clock to output in high-z [15, 20, 25] 2 3.5 2 3.5 2 3.5 2 3.5 ns t oeq oe to output valid [26] v ccq =3.3v 3.5 3.5 3.5 4.0 ns v ccq =2.5v 4.5 4.5 4.5 5.0 ns t oelz oe to output in low-z [15, 20, 25] 0 0 0 0 ns t oehz oe to output in high-z [15, 20, 25] 3.5 3.5 3.5 3.5 ns set-up times t s address, controls and data in [27] 1.5 1.5 1.8 2.0 ns hold times t h address, controls and data in [27] 0.5 0.5 0.5 0.5 ns notes: 24. test conditions as specified with the output loading as shown in ac test loads unless otherwise noted. 25. at any given temperature and voltage condition, t kqhz is less than t kqlz and t oehz is less than t oelz . 26. oe is a ? don ? t care ? when a byte write enable is sampled low. 27. this is a synchronous device. all synchronous inputs must meet specified set-up and hold time, except for ? don ? t care ? as defined in the truth table.
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 22 timing diagrams read timing [28, 29] notes: 28. for x18 product, there are only bwa and bwb for byte write control. 29. ce active in this timing diagram means that all chip enables ce , ce 2 , and ce 2 are active. ce 2 is only available for ta package version. clk adsp# adsc# address bwa#, bwb#, bwc#, bwd#, [29] bwe#, gw# ce# [30] adv# oe# dq a1 a2 q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a2+1) q(a2+2) t kq t kqlz t oelz t kq t s t h t kh t kl t kc t oeq single read burst read t s t h t s t h
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 23 write timing timing diagrams (continued) clk adsp# adsc# address bwa#, bwb#, bwc#, bwd#, [29] bwe# ce# [30] adv# oe# dq a1 a2 d(a2) d(a2+2) d(a2+3) d(a3) d(a3+1) d(a3+2) t s t h gw# a3 d(a1) d(a2+2) t kqx t oehz q d(a2+2) single write burst write burst write t h t s t h t s
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 24 read/write timing timing diagrams (continued) clk adsp# adsc# address bwa#, bwb#, bwc#, bwd#, [29] bwe#, gw# ce# [30] adv# oe# dq a1 a2 a3 q(a1) q(a2) t s t h a4 d(a3) q(a4) q(a4+1) q(a4+2) q(a4+3) d(a5) d(a5+1) single write burst read burst write single reads a5 t s t h ordering information speed (mhz) ordering code package name package type operating range 150 cy7c1361a-150ac a101 100-lead thin quad flat pack commercial gvt71256b36ta-6 cy7c1361a-150ajc gvt71256b36t-6 cy7c1361a-150bgc bg119 119-ball bga gvt71256b36b-6 133 cy7c1361a-133ac a101 100-lead thin quad flat pack commercial gvt71256b36ta-6.5 cy7c1361a-133ajc gvt71256b36t-6.5 cy7c1361a-133bgc bg119 119-ball bga gvt71256b36b-6.5
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 25 117 cy7c1361a-117ac a101 100-lead thin quad flat pack commercial gvt71256b36ta-7 cy7c1361a-117ajc gvt71256b36t-7 CY7C1361A-117BGC bg119 119-ball bga gvt71256b36b-7 100 cy7c1361a-100ac a101 100-lead thin quad flat pack commercial gvt71256b36ta-8 cy7c1361a-100ajc gvt71256b36t-8 cy7c1361a-100bgc bg119 119-ball bga gvt71256b36b-8 150 cy7c1363a-150ac a101 100-lead thin quad flat pack commercial gvt71512b36ta-6 cy7c1363a-150ajc gvt71512b36t-6 cy7c1363a-150bgc bg119 119-ball bga gvt71512b36b-6 133 cy7c1363a-133ac a101 100-lead thin quad flat pack commercial gvt71512b36ta-6.5 cy7c1363a-133ajc gvt71512b36t-6.5 cy7c1363a-133bgc bg119 119-ball bga gvt71512b36b-6.5 117 cy7c1363a-177ac a101 100-lead thin quad flat pack commercial gvt71512b36ta-7 cy7c1363a-177ajc gvt71512b36t-7 cy7c1363a-177bgc bg119 119-ball bga gvt71512b36b-7 100 cy7c1363a-100ac a101 100-lead thin quad flat pack commercial gvt71512b36ta-8 cy7c1363a-100ajc gvt71512b36t-8 cy7c1363a-100bc bg119 119-ball bga gvt71512b36b-8 document #: 38-00991-** ordering information (continued) speed (mhz) ordering code package name package type operating range
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 26 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1361a/gvt71256b36 cy7c1363a/gvt71512b18 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 119-lead fbga (14 x 22 x 2.4 mm) bg119 51-85115

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